FIG. 1 shows an exemplary High Electron Mobility Transistor (HEMT) device 100. The exemplary HEMT of FIG. 1 includes a gate electrode 102, a source electrode 103 and a drain electrode 104. The gate, source and drain electrodes 102-104 are typically made of a metal or metal alloy, such as copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof, metal nitrides such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof, metal silicide such as titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof, metal silicon nitride such as titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof, metal carbide such as titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AlC), or combinations thereof, or metal carbon nitride such as tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof. Other suitable materials may be used in other embodiments such as conductive metal oxides (e.g., ruthenium oxide).
A contact metal layer 105 is disposed underneath the source and drain electrodes 103, 104. The contact metal layer 105 makes physical contact to the underlying semiconductor “stack” 106 and serves as a physical interface between the metallic source/drain electrodes 103, 104 and the semiconductor stack 106. The cap layer 107 is a highly (e.g., degeneratively) doped semiconductor layer. Similar to silicides in MOSFET devices, the highly doped cap layer 107 serves to reduce/minimize the electrical resistance associated with the construction of a metal electrode upon semiconductor material.
Beneath the cap layer 107 is an etch stop layer 108. During construction of the HEMT, the semiconductor stack 106 is constructed by forming a buffer layer 111 on a substrate layer 112. Then, a channel layer 110 is formed on the buffer layer, a barrier layer 109 is formed on the channel layer 110 and the etch stop layer 108 is formed on the barrier layer 109. The cap layer is then formed on the etch stop layer. More pertinent features of the materials of the semiconductor stack 106 are described in more detail below.
Once the stack 106 is constructed, the contact metal layer 105 is formed. Using lithographic techniques, the contact metal 105 is patterned and etched to expose the underlying cap layer 107 in the region of the device where the gate will be formed. The exposed cap layer 107 material in the gate region of the device is then etched. The depth of the etch is limited to the surface of the etch stop layer 108. A layer of insulation 113 is formed over the device. A subsequent layer of photoresist is patterned to expose the underlying insulation 113 in the gate region. The exposed insulation 113 and immediately underlying etch stop 108 and barrier 109 layers are etched to form a trench for the device's recessed gate. Gate material 102 is subsequently deposited in the trench to form the recessed gate 102. The insulation is etched again over the source/drain region to expose the underlying contact metal 105. Source/drain electrodes 103/104 are then formed on the exposed contact metal.
The insulation at the levels of the contact metal 105 and cap 107 layers can be replaced with an air gap by polishing the gate metal and a first layer of insulation (not shown) to the surface of the contact metal 105 (this leaves the first insulation only at the levels of the contact 105 and cap 107 layers with a plug of recessed gate metal therein). A second layer of insulation is then coated over the wafer. Photoresist is coated on the wafer and patterned. The second layer of insulation is then etched to form openings above the gate metal plug. A gate electrode that makes contact to the gate metal plug is then formed on the second layer of insulation. The first layer of dielectric is then etched from the tip ends of the gate (e.g., by a wet etch) to form the air gap.
The semiconductor stack 106 is a heterostructure composed of layers of different semiconductor materials. Both the barrier 109 and buffer 111 layers have a larger energy band gap than the channel layer 110 to contain carriers within the channel layer 110 when the device is active thereby forming a high mobility conductive channel that extends along the channel layer 110 (notably, the conductive channel is also formed with the help of an appropriate voltage on the gate electrode 102).
According to one approach, both the barrier 109 and buffer 111 layers are made of Indium Aluminum Arsenide (InAlAs) and the channel layer 110 is made of Indium Gallium Arsenide (InGaAs) (notably, the ratio of the column III element to the column V element in III-V material for semiconductor devices is typically 1:1). Also, both the substrate 112 and etch stop 108 layers are made of Indium Phosphide (InP). The cap layer 107 may be made of Indium Gallium Arsenide or Indium Aluminum Arsenide. The contact metal may be made of copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof, metal nitrides such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof, metal silicide such as titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof, metal silicon nitride such as titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof, metal carbide such as titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AlC), or combinations thereof, or metal carbon nitride such as tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof. Other suitable materials may be used in other embodiments such as conductive metal oxides (e.g., ruthenium oxide).
The source/drain electrodes may be made of any of copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof, metal nitrides such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof, metal silicide such as titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof, metal silicon nitride such as titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof, metal carbide such as titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AlC), or combinations thereof, or metal carbon nitride such as tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof. Other suitable materials may be used in other embodiments such as conductive metal oxides (e.g., ruthenium oxide).
The gate material may be any of copper (Cu), gold (Au), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), nickel (Ni), cobalt (Co), rhodium (Rh), ruthenium (Ru), palladium (Pd), hafnium (Hf), zirconium (Zr), or aluminum (Al), or combinations thereof, metal nitrides such as titanium nitride (TiN), tungsten nitride (WN), or tantalum nitride (TaN), or combinations thereof, metal silicide such as titanium silicide (TiSi), tungsten silicide (WSi), tantalum silicide (TaSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel silicide (NiSi), or combinations thereof, metal silicon nitride such as titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), or combinations thereof, metal carbide such as titanium carbide (TiC), zirconium carbide (ZrC), tantalum carbide (TaC), hafnium carbide (HfC), or aluminum carbide (AlC), or combinations thereof, or metal carbon nitride such as tantalum carbon nitride (TaCN), titanium carbon nitride (TiCN), or combinations thereof. Other suitable materials may be used in other embodiments such as conductive metal oxides (e.g., ruthenium oxide).
Alternate schemes of materials may be used for the semiconductor stack. For instance, the InAlAs/InGaAs/InAlAs barrier/channel/buffer structure may be replaced with any of the following schemes: AlGaAs/GaAs/AlGaAs; or, InP/InGaAs/InP; or, InAlSb/InSb/InAlSb. Likewise, the etch stop layer 108 may be composed of InP, AlSb, and the substrate may be composed of Si, Ge, GaAs or InP. Fabrication of the individual layers is typically performed with some type of epitaxy (such as Molecular Beam Epitaxy (MBE), Vapor Phase Epitaxy (VPE), Metal-Organic Chemical Vapor Deposition (MOCVD) or Liquid Phase Expitaxy (LPE)) in order to substantially preserve a particular crystal lattice structure across the heterostructure boundaries.
In operation, carriers flow from the source electrode 103, through the contact metal 105, cap 107, etch stop 108 and barrier 109 layers into the channel layer 110. Once in the channel layer's high mobility conductive channel, the carriers flow within the channel layer 110 beneath the gate 102 and “up” into the barrier 109, etch stop 108, cap 107 and contact 105 layers associated with the drain electrode 104.
A few challenges exist with respect to the above-described HEMT carrier flow. In particular, although the carriers experience a high mobility—and therefore lower resistance—path along the channel layer 110, in contrast, the pathway through the contact/cap/etch stop/barrier structure underneath both the source and drain electrodes 103, 104 may present a number of parasitic resistances that diminish the overall performance of the transistor.